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  may 2006 rev 8 1/74 74 str71xf arm7tdmi? 32-bit mcu wi th flash, usb, can 5 timers, adc, 10 communications interfaces core ? arm7tdmi 32-bit risc cpu ? 59 mips @ 66 mhz from sram ? 45 mips @ 50 mhz from flash memories ? up to 256kbytes flash program memory (10 kcycles endurance, 20 yrs retention) ? 16k bytes flash data memory (100 kcycles endurance, 20 yrs retention) ? up to 64 kbytes ram ? external memory interface (emi) for up to 4 banks of sram, flash, rom ? multi-boot capability clock, reset and supply management ? 3.0 to 3.6v application supply and i/os ? internal 1.8v regulator for core supply ? clock input from 0 to 16.5 mhz ? embedded rtc oscillator running from external 32 khz crystal ? embedded pll for cpu clock ? realtime clock for clock-calendar function ? 5 power saving modes: slow, wait, lpwait, stop and standby modes nested interrupt controller ? fast interrupt handling with multiple vectors ? 32 vectors with 16 irq priority levels ? 2 maskable fiq sources up to 48 i/o ports ? 30/32/48 multifunctional bidirectional i/os ? up to 14 ports with interrupt capability 5 timers ? 16-bit watchdog timer ? 3 16-bit timers with 2 input captures, 2 output compares, pwm and pulse counter ? 16-bit timer for timebase functions 10 communications interfaces ?2 i 2 c interfaces (1 multiplexed with spi) ? 4 uart asynchronous serial interfaces ? smart card iso7816-3 interface on uart1 ? 2 bspi synchronous serial interfaces ? can interface (2.0b active) ? usb full speed (12mbit/s) device function with suspend and resume ? hdlc synchronous communications 4-channel 12-bit a/d converter ? sampling frequency up to 1khz ? conversion range: 0 to 2.5v development tools support lqfp64 10 x 10 lqfp144 20 x 20 lfbga64 8 x 8 x 1.7 lfbga144 10 x 10 x 1.7 lfbga64 8 x 8 x 1.7 table 1. device summary features str710 fz1 str710 fz2 str710 rz str711 fr0 str711 fr1 str711 fr2 str712 fr0 str712 fr1 str712 fr2 str715 frx flash - kbytes 128+16 256+16 0 64+16 128+ 16 256+16 64+16 128+16 256+16 64+16 ram - kbytes 32 64 64 16 32 64 16 32 64 16 peripheral functions can, emi, usb, 48 i/os usb, 30 i/os can, 32 i/os 32 i/os operating voltage 3.0 to 3.6v operating temp. -40 to +85c packages t =lqfp144 20 x 20 h =lfbga144 10 x10 t =lqfp64 10 x10 / h =lfbga64 8 x 8 x 1.7 www.st.com
contents str71xf 2/74 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4 pin description for 144-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.5 pin description for 64-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.6 external connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.7 i/o port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.8 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.3.1 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.3.2 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.3.3 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.3.4 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.3.5 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.3.6 tim timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2.3.7 emi - memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.3.8 communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.3.9 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
str71xf contents 3/74 4 product history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 note: for detailed information on the str710 microcontroller memory, registers and peripherals, please refer to the str710 reference manual.
introduction str71xf 4/74 1 introduction this datasheet provides the str71x ordering information, mechanical and electrical device characteristics. for complete information on the str710 microcontroller memory, registers and peripherals. please refer to the str710 reference manual. for information on programming, erasing and protection of the internal flash memory please refer to the str7 flash programming reference manual for information on the arm7tdmi core please refer to the arm7tdmi technical reference manual. 1.1 overview arm ? core with embedded flash & ram the str710 series is a family of arm-powered 32-bit microcontrollers with embedded flash and ram. it combines the high per formance arm7tdmi cpu with an extensive range of peripheral func tions and enhanced i/o capabilitie s. str71xf devices have on-chip high-speed single voltage flash memory and high-speed ram. str710r devices have high-speed ram but no internal flash. the str710 family has an embedded arm core and is therefore compatible with all arm tools and software. extensive tools support stmicroelectronics? 32-bit, arm core-based mi crocontrollers are supported by a complete range of high-end and low-cost development tools to meet the needs of application developers. this extensive line of hardware/software tools includes starter kits and complete development packages all tailored for st?s arm core-based mcus. the range of development packages includes third-party solutions that come complete with a graphical development environment and an in-circuit emulator/programmer featuring a jtag application interface. these support a range of embedded operating systems (os), while several royalty-free oss are also available. for more information, please refer to st mcu site http://www.st.com/mcu package choice: low pin-count 64-pin or feature-rich 144-pin lqfp or bga the str710 family is available in 5 main versions. the 144-pin versions have the full set of a ll features including can, usb and external memory interface (emi). str710f: 144-pin bga or lqfp with can, usb and emi str710r: flashless 144-pin bga or lqfp with can, usb and emi (no internal flash memory)
str71xf introduction 5/74 the three 64-pin versions (bga or lqfp) do not include external memory interface. str715f: 64-pin bga or lqfp without can or usb str711f: 64-pin bga or lqfp with usb str712f: 64-pin bga or lqfp with can high speed flash memory (str71xf) the flash program memory is organized in tw o banks of 32-bit wide burst flash memories enabling true read-while-write (rww) operation. device bank 0 is up to 256 kbytes in size, typically for the application program code. bank 1 is 16k bytes, typically used for storing data constants. both banks are accessed by the cpu with zero wait states @ 33 mhz bank 0 memory endurance is 10k write/eras e cycles and bank 1 endurance is 100k write/erase cycles. data retention is 20 years on both banks. the two banks can be accessed independently in read or write. flash memory can be accessed in two modes: burst mode: 64-bit wide memory access at up to 50 mhz. direct 32-bit wide memory access for deterministic operation at up to 33 mhz. the str7 embedded flash memory can be programmed using in-circuit programming or in-application programming. iap (in-application programming): the iap is the ability to re -program the flash memory of a microcontroller while the user program is running. icp (in-circuit programming): the icp is the ability to prog ram the flash memory of a microcontroller using jtag protocol while the device is mounted on the user application board. the flash memory can be protected against different types of unwanted access (read/write/erase). there are two types of protection: sector write protection flash debug protection (locks jtag access) refer to the str7 flash programming reference manual for details. optional external memory (str710) the non-multiplexed 16-bit data/24-bit address bus available on the str710 (144-pin) supports four 16-mbyte banks of external memory. wait states are programmable individually for each bank allowing different memory types (flash, eprom, rom, sram etc.) to be used to store programs or data. figure 1 shows the general block diagram of the device family. flexible power management to minimize power consumption, you can program the str710 to switch to slow, wait, lpwait (low power wait), stop or standby mode depending on the current system activity in the application. flexible clock control two external clock sources can be used, a main clock and a 32 khz backup clock. the embedded pll allows the internal system clock (up to 66 mhz) to be generated from a main clock frequency of 16 mhz or less. the pll output frequency can be programmed using a wide selection of multipliers and dividers . the microcontrolle r core, apb1 and apb2 peripherals are in separate clock domains and can be programmed to run at different frequencies during application runtime. the clock to each peripheral is gated with an
introduction str71xf 6/74 individual control bit to optimize power usage by turning off peripherals any time they are not required. voltag e regulators the str710 requires an external 3.0-3.6v power supply. there are two internal voltage regulators for generating the 1.8v power supply for the core and peripherals. the main vr is switched off during low power operation. low voltage detectors each voltage regulator has an embedded lvd that monitors the internal 1.8v supply. if the regulated voltag e drops below a certain threshold, the lvd will reset the str710. this enhances the security of the system by preventing the mcu from going into an unpredictable state. an external reset circuit must be used to provide the reset at v 33 power-up. it is not sufficient to rely on the reset generated by the lvd in this case. this is because lvd operation is guaranteed only when v 33 is within the specification. 1.2 on-chip peripherals can interface (str710 and str712) the can module is compliant with the can spec ification v2.0 part b (active). the bit rate can be programmed up to 1 mbaud. usb interface (str710 and str711) the full-speed usb interface is usb v2.0 compliant and provides up to 16 bidirectional/32 unidirectional endpoints, up to 12 mb/s (full- speed), support for bulk transfer, isochronous transfers and usb suspend/resume functions. standard timers each of the four timers have a 16-bit free-running counter with 7-bit prescaler three timers each provide up to two input capture/output compare functions, a pulse counter function, and a pwm channel with selectable frequency. the fourth timer is not connected to the i/o ports. it can be used by the application software for general timing functions. realtime clock (rtc) the rtc provides a set of continuously running counters driven by the 32 khz external crystal. the rtc can be used as a general timebase or clock/calendar/alarm function. when the str710 is in standby mode the rtc can be kept running, powered by the low power voltage regulator and driven by the 32 khz external crystal. uarts the 4 uarts allow full duplex, asynchronous, communications with external devices with independently programmable tx and rx baud rates up to 1.25 mb/s. smart card interface uart1 is configurable to function either as a general purpose uart or as an asynchronous smart card interface as defined by iso 7816-3. it includes smart card clock generation and provides support features for synchronous cards.
str71xf introduction 7/74 buffered serial peripheral interfaces (bspi) each of the two spis allow full duplex, synchronous communications with external devices, master or slave communication at up to 5.5mb/s in master mode and 4 mb/s in slave mode. i 2 c interfaces the two i 2 c interfaces provide multi-master and slave functions, support normal and fast i 2 c mode (400 khz) and 7 or 10-bit addressing modes. one i 2 c interface is multiplexed with one spi, so either 2xspi+1x i 2 c or 1xspi+2x i 2 c may be used at a time. hdlc interface the high level data link controller (hdlc) unit supports full duplex operation and nrz, nrzi, fm0 or manchester protocols. it has an internal 8-bit baud rate generator. a/d converter the analog to digital converter, converts in single channel or up to 4 channels in single- shot or round robin mode. resolution is 12-bit with a sampling frequency of up to 1 khz. the input voltage range is 0-2.5v. watchdog the 16-bit watchdog timer protects the application against hardware or software failures and ensures recovery by generating a reset. i/o ports the 48 i/o ports are programmable as inputs or outputs. external interrupts up to 14 external interrupts are available for application use or to wake-up the application from stop mode.
introduction str71xf 8/74 figure 1. str710 block diagram apb bus usbdp usbdn p0[15:0] i/o port 0 flash* program memory 64/128/256k i2c0 i2c1 bspi0 bspi1 uart0 uart1 / uart2 uart3 usb can hdlc apb bridge 1 apb bridge 2 apb bus timer1 timer2 timer3 rtc ext int (xti) watchdog interrupt ctl(eic) a/d power supply prccu/pll ram 16/32/64k jtag arm7tdmi cpu ext. mem. stdby 2 af 4 af 4 af 2 af 3 af 2 af 2 af 2 af 3 af 4 af 4 af 2 af 4 af a[19:0] d[15:0] rdn wen[1:0] rtcxto rtcxti wakeup jtdi jtck jtms jtrst jtdo ck ckout rstin v18[1:0] v33[6:0] vss[9:0] v18bkp 14 af osc dbgrqs booten vreg avdd avss p1[15:0] i/o port 1 p2[15:0] i/o port 2 timer0 arm7 native bus cs[3:0) 2 af 1 af af: alternate function on i/o port pin interface (emi) a[23:20] (af) smartcard 16k data flash* *flash present in str710f, not in str710r
str71xf introduction 9/74 1.3 related documentation available from www.arm.com: arm7tdmi technical reference manual available from http://www.st.com: str71x reference manual str7 flash programming reference manual an1774 - str710 software development getting started an1775 - str710 hardware development getting started an1776 - str710 enhanced interrupt controller an1777 - str710 memory mapping an1780 - real time clock with str710 an1781 - four 7 segment display drive using the str710 the above is a selected list only, a full list str71x application notes can be viewed at http://www.st.com .
introduction str71xf 10/74 1.4 pin description for 144-pin packages figure 2. str710 lqfp pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 p0.10/u1.rx/u1.tx/scdata rdn p0.11/u1.tx/boot.1 p0.12/scclk vss v33 p2.0/csn.0 p2.1/csn.1 p0.13/u2.rx/t2.ocmpa p0.14/u2.tx/t2.icapa p2.2/csn.2 p2.3/csn.3 p2.4/a.20 p2.5/a.21 p2.6/a.22 booten p2.7/a.23 p2.8 n.c. n.c. vss v33 p2.9 p2.10 p2.11 p2.12 p2.13 p2.14 p2.15 jtdi jtms jtck jtdo jtrstn nu test p1.14/hrxd/i0.sda p1.13/hclk/i0.scl p1.10/usbclk p1.9 v33 vss a.4 a.3 a.2 a.1 a.0 d.15 d.14 d.13 d.12 d.11 d.10 usbdn usbdp p1.12/cantx p1.11/canrx n.c. p1.8 p1.7/t1.ocmpa vssio-pll v33io-pll d.9 d.8 d.7 d.6 d.5 p1.6/t1.ocmpb p1.5/t1.icapb p1.4/t1.icapa p1.3/t3.icapb/ain.3 p1.2/t3.ocmpa/ain.2 n.c. test n.c. v33io-pll n.c. vssio-pll n.c. dbgrqs ckout ck p0.15/wakeup n.c. rtcxti rtcxto stdby rstin n.c. vssbkp v18bkp n.c. n.c. v18 vss18 n.c. d.0 d.1 d.2 d.3 d.4 avdd avss n.c. n.c. n.c. p1.0/t3.ocmpb/ain.0 p1.1/t3.icapa/ain.1 p0.9/u0.tx/boot.0 p0.8/u0.rx/u0.tx p0.7/s1.ssn p0.6/s1.sclk p0.5/s1.mosi vss v33 wen.0 wen.1 a.19 a.18 a.17 a.16 a.15 a.14 v18 vss18 p0.4/s1.miso p0.3/s0.ssn/i1.sda p0.2/s0.sclk/i1.scl p0.1/s0.mosi/u3.rx p0.0/s0.miso/u3.tx a.13 a.12 a.11 a.10 a.9 a.8 a.7 a.6 a.5 v33 vss p1.15/htxd n.c. n.c. lqfp144
str71xf introduction 11/74 legend / abbreviations for ta bl e 3 : type: i = input, o = output, s = supply, hiz= high impedance, in/output level: c = cmos 0.3v dd /0.7v dd c t = cmos 0.3v dd /0.7v dd with input trigger t t = ttl 0.8v/2v with input trigger c/t = programmable levels: cmos 0.3v dd /0.7v dd or ttl 0.8v / 2v port and control configuration: input: pu/pd= software enabled internal pull-up or pull down pu= in reset state, the internal 100k ? weak pull-up is enabled. pd = in reset state, the internal 100k ? weak pull-down is enabled. output: od = open drain (logic level) pp = push-pull t = true od, (p-buffer and protection diode to v dd not implemented), 5v tolerant. table 2. str710 bga ball connections abcdefghjklm 1 p0.10 p2.0 p2.1 vss p2.2 p2.6 boot en p2.12 p2.13 p2.15 jtdi n.c. 2 vss rdn p0.11 v33 p2.3 p2.8 p2.9 jtms jtrst n test test n.c. 3 v33 p0.9 p0.12 p0.13 p2.4 n.c. p2.10 jtck nu v33 n.c. dbg rqs 4 p0.6 p0.7 p0.8 p0.14 p2.5 n.c. p2.11 jtdo ck ckout vssio- pll n.c. 5 a.19 wen.1 wen.0 p0.5 p2.7 vss p2.14 n.c. rtcx- to rtcxti n.c. p0.15 6 p0.3 a.15 a.16 a.17 a.18 v33 v18 n.c. n.c. v18bk p vss bkp stdby 7 p0.2 p0.1 p0.4 vss18 v18 a.14 d.12 d.1 d.0 nc vss18 rstin 8 a.9 a.10 a.11 a.13 p0.0 a.0 d.11 p1.12/ cantx n.c. avss d.3 d.2 9 vss v33 a.5 a.6 v33 d.15 d.10 p1.8 d.9 p1.0 n.c. n.c. 10 a.8 n.c. p1.15 p1.13 vss d.14 usbdn p1.7 d.8 p1.5 p1.1 d.4 11 a.7 n.c. p1.14 p1.10 a.2 d.13 usbdp vss d.5 p1.4 p1.3 avdd 12 a.12 a.4 a.3 p1.9 a.1 p1.11/ canrx n.c. v33io- pll p1.6 d.7 d.6 p1.2
introduction str71xf 12/74 table 3. str710 pin description pin n pin name type reset state 1) input output active in stdby main function (after reset) alternate function lqfp144 bga144 input level interrupt capability od pp 1a1 p0.10/u1.rx/ u1.tx/ sc.data i/o pd c t x 4ma t port 0.10 uart1: receive data input uart1: transmit data output. note: this pin may be used for smartcard datain/dataout or single wire uart (half duplex) if programmed as alternate function output. the pin will be tri-stated except when uart transmission is in progress 2b2rd o 5) x external memory interface: active low read signal for external memory. it maps to the oe_n input of the external components. 3c2 p0.11/boot.1 /u1.tx i/o pd c t 4ma x x port 0.11 select boot configuration input uart1: transmit data output. 4 c3 p0.12/sc.clk i/o pd c t 4ma x x port 0.12 smartcard reference clock output 5d1v ss s ground voltage for digital i/os 4) 6d2v 33 s supply voltage for digital i/os 4) 7 b1 p2.0/cs .0 i/o 8) c t 8ma x x port 2.0 external memory interface: select memory bank 0 output note: this pin is forced to output push-pull 1 mode at reset to allow boot from external memory 8 c1 p2.1/cs .1 i/o pu 2) c t 8ma x x port 2.1 external memory interface: select memory bank 1 output 9d3 p0.13/u2.rx/ t2.ocmpa i/o pu c t x 4ma x x port 0.13 uart2: receive data input timer2: output compare a output 10 d4 p0.14/u2.tx/ t2.icapa i/o pu c t 4ma x x port 0.14 uart2: transmit data output timer2: input capture a input 11 e1 p2.2/cs .2 i/o pu 2) c t 8ma x x port 2.2 external memory interface: select memory bank 3 output 12 e2 p2.3/cs .3 i/o pu 2) c t 8ma x x port 2.3 external memory interface: select memory bank 4 output
str71xf introduction 13/74 13 e3 p2.4/a.20 i/o pd 3) c t 8ma x x port 2.4 external memory interface: address bus 14 e4 p2.5/a.21 i/o pd 3) c t 8ma x x port 2.5 15 f1 p2.6/a.22 i/o pd 3) c t 8ma x x port 2.6 16 g1 booten i c t boot control input. enables sampling of boot[1:0] pins 17 e5 p2.7/a.23 i/o pd 3) c t 8ma x x port 2.7 external memory interface: address bus 18 f2 p2.8 i/o pu c t x 4ma x x port 2.8 external interrupt int2 19 f3 n.c. not connected (not bonded) 20 f4 n.c. not connected (not bonded) 21 f5 v ss s ground voltage for digital i/os 4) 22 f6 v 33 s supply voltage for digital i/os 4) 23 g2 p2.9 i/o pu c t x 4ma x x port 2.9 external interrupt int3 24 g3 p2.10 i/o pu c t x 4ma x x port 2.10 external interrupt int4 25 g4 p2.11 i/o pu c t x 4ma x x port 2.11 external interrupt int5 26 h1 p2.12 i/o pu c t 4ma x x port 2.12 27 j1 p2.13 i/o pu c t 4ma x x port 2.13 28 g5 p2.14 i/o pu c t 4ma x x port 2.14 29 k1 p2.15 i/o pu c t 4ma x x port 2.15 30 l1 jtdi i t t jtag data input. external pull-up required. 31 h2 jtms i t t jtag mode selection input. external pull-up required. 32 h3 jtck i c jtag clock input. external pull-up or pull-down required. 33 h4 jtdo o 8ma x jtag data output. note: reset state = hiz. 34 j2 jtrst i t t jtag reset input. external pull-up required. 35 j3 nu reserved, must be forced to ground. 36 k2 test reserved, must be forced to ground. 37 m1 n.c. not connected (not bonded) 38 l2 test reserved, must be forced to ground. 39 l3 n.c. not connected (not bonded) table 3. str710 pin description pin n pin name type reset state 1) input output active in stdby main function (after reset) alternate function lqfp144 bga144 input level interrupt capability od pp
introduction str71xf 14/74 40 k3 v 33io-pll s supply voltage for digital i/o circuitry and for pll reference 41 m4 n.c. not connected (not bonded) 42 l4 v ssio-pll s ground voltage for digital i/o circuitry and for pll reference 4) 43 m2 n.c. not connected (not bonded) 44 m3 dbgrqs i c t debug mode request input (active high) 45 k4 ckout o 8ma x clock output (f pclk2 ) note: enabled by ckdis register in apb bridge 2 46 j4 ck i c reference clock input 47 m5 p0.15/ wakeup it t xx port 0.15 wakeup from standby mode input. note: this port is input only. 48 l5 n.c. not connected (not bonded) 49 k5 rtcxti realtime clock input and input of 32 khz oscillator amplifier circuit 50 j5 rtcxto output of 32 khz oscillator amplifier circuit 51 m6 stdby i/o c t 4ma x x input: hardware standby mode entry input active low. caution: external pull-up to v 33 required to select normal mode. output: standby mode active low output following software standby mode entry. note : in standby mode all pins are in high impedance except those marked active in stdby 52 m7 rstin ic t x reset input 53 h5 n.c. not connected (not bonded) 54 l6 v ssbkp s x stabilization for low power voltage regulator. 55 k6 v 18bkp sx stabilization for low power voltage regulator. requires external capacitors of at least 1f between v 18bkp and v ss18bkp . see figure 5 . note: if the low power voltage regulator is bypassed, this pin can be connected to an external 1.8v supply. 56 j6 n.c. not connected (not bonded) 57 h6 n.c. not connected (not bonded) 58 g6 v 18 s stabilization for main voltage regulator. requires external capacitors of at least 10f + 33nf between v 18 and v ss18 . see figure 5 . table 3. str710 pin description pin n pin name type reset state 1) input output active in stdby main function (after reset) alternate function lqfp144 bga144 input level interrupt capability od pp
str71xf introduction 15/74 59 l7 v ss18 s stabilization for main voltage regulator. 60 k7 n.c. not connected (not bonded) 61 j7 d.0 i/o 6) 8ma external memory interface: data bus 62 h7 d.1 i/o 6) 8ma 63 m8 d.2 i/o 6) 8ma 64 l8 d.3 i/o 6) 8ma 65 m10 d.4 i/o 6) 8ma 66 m11 v dda s supply voltage for a/d converter 67 k8 v ssa s ground voltage for a/d converter 68 j8 n.c. not connected (not bonded) 69 m9 n.c. not connected (not bonded) 70 l9 n.c. not connected (not bonded) 71 k9 p1.0/t3.ocm pb/ain.0 i/o pu c t 4ma x x port 1.0 timer 3: output compare b adc: analog input 0 72 l10 p1.1/t3.icap a/t3.extclk/ ain.1 i/o pu c t 4ma x x port 1.1 timer 3: input capture a or external clock input adc: analog input 1 73 m12 p1.2/t3.ocm pa/ain.2 i/o pu c t 4ma x x port 1.2 timer 3: output compare a adc: analog input 2 74 l11 p1.3/t3.icap b/ain.3 i/o pu c t 4ma x x port 1.3 timer 3: input capture b adc: analog input 3 75 k11 p1.4/t1.icap a/t1.extclk i/o pu c t 4ma x x port 1.4 timer 1: input capture a timer 1: external clock input 76 k10 p1.5/t1.icap b i/o pu c t 4ma x x port 1.5 timer 1: input capture b 77 j12 p1.6/t1.ocm pb i/o pu c t 4ma x x port 1.6 timer 1: output compare b 78 j11 d.5 i/o 6) 8ma external memory interface: data bus 79 l12 d.6 i/o 6) 8ma 80 k12 d.7 i/o 6) 8ma 81 j10 d.8 i/o 6) 8ma 82 j9 d.9 i/o 6) 8ma table 3. str710 pin description pin n pin name type reset state 1) input output active in stdby main function (after reset) alternate function lqfp144 bga144 input level interrupt capability od pp
introduction str71xf 16/74 83 h12 v 33io-pll s supply voltage for digital i/o circuitry and for pll reference 4) 84 h11 v ssio-pll s ground voltage for digital i/o circuitry and for pll reference 4) 85 h10 p1.7/t1.ocm pa i/o pu c t 4ma x x port 1.7 timer 1: output compare a 86 h9 p1.8 i/o pd c t 4ma x x port 1.8 87 g12 n.c. not connected (not bonded) 88 f12 p1.11/canrx i/o pu c t x 4ma x x port 1.11 can: receive data input note: on str710 and str712 only 89 h8 p1.12/cantx i/o pu c t 4ma x x port 1.12 can: transmit data output note: on str710 and str712 only 90 g11 usbdp i/o c t usb bidirectional data (data +). reset state = hiz note: on str710 and str711 only this pin requires an external pull-up to v 33 to maintain a high level. 91 g10 usbdn i/o c t usb bidirectional data (data -). reset state = hiz note: on str710 and str711 only. 92 g9 d.10 i/o 6) 8ma external memory interface: data bus 93 g8 d.11 i/o 6) 8ma 94 g7 d.12 i/o 6) 8ma 95 f11 d.13 i/o 6) 8ma 96 f10 d.14 i/o 6) 8ma 97 f9 d.15 i/o 6) 8ma 98 f8 a.0 o 7) 8ma x external memory interface: address bus 99 e12 a.1 o 7) 8ma x 100 e11 a.2 o 7) 8ma x 101 c12 a.3 o 7) 8ma x 102 b12 a.4 o 7) 8ma x 103 e10 v ss s ground voltage for digital i/o circuitry 4) 104 e9 v 33 s supply voltage for digital i/o circuitry 4) 105 d12 p1.9 i/o pd c t 4ma x x port 1.9 106 d11 p1.10/ usbclk i/o pd c/ t 4ma x x port 1.10 usb: 48 mhz clock input table 3. str710 pin description pin n pin name type reset state 1) input output active in stdby main function (after reset) alternate function lqfp144 bga144 input level interrupt capability od pp
str71xf introduction 17/74 107 d10 p1.13/hclk/ i0.scl i/o pd c t x 4ma x x port 1.13 hdlc: reference clock input i2c clock 108 c11 p1.14/hrxd/ i0.sda i/o pu c t x 4ma x x port 1.14 hdlc: receive data input i2c serial data 109 b11 n.c. not connected (not bonded) 110 b10 n.c. not connected (not bonded) 111 c10 p1.15/htxd i/o pu c t 4ma x x port 1.15 hdlc: transmit data output 112 a9 v ss s ground voltage for digital i/o circuitry 4) 113 b9 v 33 s supply voltage for digital i/o circuitry 4) 114 c9 a.5 o 7) 8ma x external memory interface: address bus 115 d9 a.6 o 7) 8ma x 116 a11 a.7 o 7) 8ma x 117 a10 a.8 o 7) 8ma x 118 a8 a.9 o 7) 8ma x 119 b8 a.10 o 7) 8ma x 120 c8 a.11 o 7) 8ma x 121 a12 a.12 o 7) 8ma x 122 d8 a.13 o 7) 8ma x 123 e8 p0.0/s0.miso /u3.tx i/o pu c t 4ma x x port 0.0 spi0 master in/slave out data uart3 transmit data output note: programming af function selects uart by default. bspi must be enabled by spi_en bit in the bootcr register. 124 b7 p0.1/s0.mosi /u3.rx i/o pu c t x4ma x x port 0.1 bspi0: master out/slave in data uart3: receive data input note: programming af function selects uart by default. bspi must be enabled by spi_en bit in the bootcr register. table 3. str710 pin description pin n pin name type reset state 1) input output active in stdby main function (after reset) alternate function lqfp144 bga144 input level interrupt capability od pp
introduction str71xf 18/74 125 a7 p0.2/s0.sclk /i1.scl i/o pu c t x4ma x x port 0.2 bspi0: serial clock i2c1: serial clock note: programming af function selects i2c by default. bspi must be enabled by spi_en bit in the bootcr register. 126 a6 p0.3/s0.ss / i1.sda i/o pu c t 4ma x x port 0.3 spi0: slave select input active low. i2c1: serial data note: programming af function selects i2c by default. bspi must be enabled by spi_en bit in the bootcr register. 127 c7 p0.4/s1.miso i/o pu c t 4ma x x port 0.4 spi1: master in/slave out data 128 d7 v ss18 s stabilization for main voltage regulator. 129 e7 v 18 s stabilization for main voltage regulator. requires external capacitors of at least 10f + 33nf between v 18 and v ss18 . see figure 5 . 130 f7 a.14 o 7) 8ma x external memory interface: address bus 131 b6 a.15 o 7) 8ma x 132 c6 a.16 o 7) 8ma x 133 d6 a.17 o 7) 8ma x 134 e6 a.18 o 7) 8ma x 135 a5 a.19 o 7) 8ma x 136 b5 we .1 o 5) 8ma x external memory interface: active low msb write enable output 137 c5 we .0 o 5) 8ma x external memory interface: active low lsb write enable output 138 a3 v 33 s supply voltage for digital i/os 4) 139 a2 v ss s ground voltage for digital i/os 4) 140 d5 p0.5/s1.mosi i/o pu c t 4ma x x port 0.5 spi1: master out/slave in data 141 a4 p0.6/s1.sclk i/o pu c t x 4ma x x port 0.6 spi1: serial clock 142 b4 p0.7/s1.ss i/o pu c t 4ma x x port 0.7 spi1: slave select input active low table 3. str710 pin description pin n pin name type reset state 1) input output active in stdby main function (after reset) alternate function lqfp144 bga144 input level interrupt capability od pp
str71xf introduction 19/74 1. the reset configuration of the i/o ports is ipupd (input pull-up/pull down). refer to table 7 on page 28 . the port bit configuration at reset is pc0=1, pc1=1, pc2=0. the port data regist er bit (pd) value depends on the pu/pd column which specifies whether the pull-up or pull-down is enabled at reset 2. in reset state, these pins configured as input pu /pd with weak pull-up enabled. they must be configured by software as alternate function (see table 7: port bit configuration table on page 28 ) to be used by the external memory interface. 3. in reset state, these pins configured as input pu/pd with weak pull-down enabled to output address 0x0000 0000 using the external memory interface. to access memory banks gr eater than 1mbyte, they need to be configured by software as alternate function (see table 7: port bit configuration table on page 28 ). 4. v 33io-pll and v 33 are internally connected. v ssio-pll and v ss are internally connected. 5. during the reset phase, these pins ar e in input pull-up state. when reset is released, they are configured as output push-pull. 6. during the reset phase, these pins ar e in input pull-up state. when reset is released, they are configured as hi-z. 7. during the reset phase, these pins are in input pull-dow n state. when reset is released, they are configured as output push-pull. 8. during the reset phase, and after reset is released, this pin is in output push-pull state. 143 c4 p0.8/u0.rx/ u0.tx i/o pd c t x4ma t port 0.8 uart0: receive data input uart0: transmit data output. note: this pin may be used for single wire uart (half duplex) if programmed as alternate function output. the pin will be tri-stated except when uart transmission is in progress 144 b3 p0.9/u0.tx/ boot.0 i/o pd c t 4ma x x port 0.9 select boot configuration input uart0: transmit data output table 3. str710 pin description pin n pin name type reset state 1) input output active in stdby main function (after reset) alternate function lqfp144 bga144 input level interrupt capability od pp
introduction str71xf 20/74 1.5 pin description for 64-pin packages figure 3. str712/str715 lqfp64 pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 p1.14/hrxd/i0.sda p1.13/hclk/i0.scl p1.10 p1.9 vss p1.12/cantx 1) p1.11/canrx 1) p1.8 p1.7/t1.ocmpa vssio-pll v33io-pll p1.6/t1.ocmpb p1.5/t1.icapb p1.4/t1.icapa p1.3/t3.icapb/ain.3 p1.2/t3.ocmpa/ain.2 v33io-pll vssio-pll ck p0.15/wakeup rtcxti rtcxto stdby rstin vssbkp v18bkp v18 vss18 avdd avss p1.0/t3.ocmpb/ain.0 p1.1/t3.icapa/ain.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p0.10/u1.rx/u1.tx/scdata p0.11/u1.tx/boot.1 p0.12/scclk vss p0.13/u2.rx/t2.ocmpa p0.14/u2.tx/t2.icapa booten vss v33 jtdi jtms jtck jtdo njtrst nu test p0.9/u0.tx/boot.0 p0.8/u0.rx/u0.tx p0.7/s1.ssn p0.6/s1.sclk p0.5/s1.mosi vss v18 vss18 p0.4/s1.miso p0.3/s0.ssn/i1.sda p0.2/s0.sclk/i1.scl p0.1/s0.mosi/u3.rx p0.0/s0.miso/u3.tx v33 vss p1.15/htxd lqfp64 1) cantx and canrx in str712f only, in str715f they are general purpose i/os.
str71xf introduction 21/74 figure 4. str711 lqfp64 pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 p1.14/hrxd/i0.sda p1.13/hclk/i0.scl p1.10/usbclk p1.9 vss usbdn usbdp p1.8 p1.7/t1.ocmpa vssio-pll v33io-pll p1.6/t1.ocmpb p1.5/t1.icapb p1.4/t1.icapa p1.3/t3.icapb/ain.3 p1.2/t3.ocmpa/ain.2 v33io-pll vssio-pll ck p0.15/wakeup rtcxti rtcxto stdby rstin vssbkp v18bkp v18 vss18 avdd avss p1.0/t3.ocmpb/ain.0 p1.1/t3.icapa/ain.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p0.10/u1.rx/u1.tx/scdata p0.11/u1.tx/boot.1 p0.12/scclk vss p0.13/u2.rx/t2.ocmpa p0.14/u2.tx/t2.icapa booten vss v33 jtdi jtms jtck jtdo njtrst nu test p0.9/u0.tx/boot.0 p0.8/u0.rx/u0.tx p0.7/s1.ssn p0.6/s1.sclk p0.5/s1.mosi vss v18 vss18 p0.4/s1.miso p0.3/s0.ssn/i1.sda p0.2/s0.sclk/i1.scl p0.1/s0.mosi/u3.rx p0.0/s0.miso/u3.tx v33 vss p1.15/htxd lqfp64 table 4. str711 bga ball connections abcdefgh 1 p0.10 p0.11 p0.12 p0.14 v33 jtck test v33io- pll 2 p0.9 vss p0.13 vss jt ms jtrstn p0.15 vssio- pll 3 p0.5 p0.7 booten jtdi nu stdby rtcxti ck 4 vss18 vss p0.8 jtdo avdd v18bkp rstin rtcxto 5 p0.2 p0.4 v18 p0.6 p1.9 p1.0 v18 vssbkp 6 v33 p0.1 p0.3 p1.13 usbdp vssio- pll avss vss18 7 vss p0.0 p1.10 usbdn p1.7 p1.6 p1.5 p1.1 8 p1.15 p1.14 vss p1.8 v33io- pll p1.4 p1.3 p1.2
introduction str71xf 22/74 1) cantx and canrx in str712f only, in str715f they are general purpose i/os. legend / abbreviations for table 6 : type: i = input, o = output, s = supply, hiz= high impedance, in/output level: c = cmos 0.3v dd /0.7v dd c t = cmos 0.8v / 2v with input trigger t t = ttl 0.3v/0.7v dd with input trigger c/t = programmable levels: cmos 0.3v dd /0.7v dd or ttl 0.8v / 2v port and control configuration: input: pu/pd= software enabled internal pull-up or pull down pu= in reset state, the internal 100k ? weak pull-up is enabled. pd = in reset state, the internal 100k ? weak pull-down is enabled. output: od = open drain (logic level) pp = push-pull t = true od, (p-buffer and protection diode to v dd not implemented), 5v tolerant. table 5. str712/715 bga ball connections abcdefgh 1 p0.10 p0.11 p0.12 p0.14 v33 jtck test v33io- pll 2 p0.9 vss p0.13 vss jtms jtrstn p0.15 vssio- pll 3 p0.5 p0.7 booten jtdi nu stdby rtcxti ck 4 vss18 vss p0.8 jtdo avdd v18bkp rstin rtcxto 5 p0.2 p0.4 v18 p0.6 p1.9 p1.0 v18 vssbkp 6 v33 p0.1 p0.3 p1.13 p1.11/ canrx 1) vssio- pll avss vss18 7 vss p0.0 p1.10 p1.12/ cantx 1) p1.7 p1.6 p1.5 p1.1 8 p1.15 p1.14 vss p1.8 v33io- pll p1.4 p1.3 p1.2
str71xf introduction 23/74 table 6. str711/str712/str715 pin description pin n pin name type reset state 1) input output active in stdby main function (after reset) alternate function lqfp64 bga64 input level interrupt capability od pp 1a1 p0.10/u1.rx/ u1.tx/ sc.data i/o pd c t x 4ma t port 0.10 uart1: receive data input uart1: transmit data output. note: this pin may be used for smartcard datain/dataout or single wire uart (half duplex) if programmed as alternate function output. the pin will be tri-stated except when uart transmission is in progress 2b1 p0.11/boot.1 /u1.tx i/o pd c t 4ma x x port 0.11 select boot configuration input uart1: transmit data output. 3 c1 p0.12/sc.clk i/o pd c t 4ma port 0.12 smartcard reference clock output 4b2v ss s ground voltage for digital i/os 2) 5c2 p0.13/u2.rx/ t2.ocmpa i/o pu c t x4ma x x port 0.13 uart2: receive data input timer2: output compare a output 6d1 p0.14/u2.tx/ t2.icapa i/o pu c t 4ma x x port 0.14 uart2: transmit data output timer2: input capture a input 7c3booten i c t boot control input. enables sampling of boot[1:0] pins 8d2v ss s ground voltage for digital i/os 2) 9e1v 33 s supply voltage for digital i/os 2) 10 d3 jtdi i t t jtag data input. external pull-up required. 11 e2 jtms i t t jtag mode selection input. external pull-up required. 12 f1 jtck i c jtag clock input. external pull-up or pull-down required. 13 d4 jtdo o 8ma x jtag data output. note: reset state = hiz. 14 f2 jtrst i t t jtag reset input. external pull-up required. 15 e3 nu reserved, must be forced to ground. 16 g1 test reserved, must be forced to ground. 17 h1 v 33io-pll s supply voltage for digital i/o circuitry and for pll reference 2) 18 h2 v ssio-pll s ground voltage for digital i/o circuitry and for pll reference 2) 19 h3 ck i c reference clock input
introduction str71xf 24/74 20 g2 p0.15/ wakeup it t xx port 0.15 wakeup from standby mode input. note: this port is input only. 21 g3 rtcxti realtime clock input and input of 32 khz oscillator amplifier circuit 22 h4 rtcxto output of 32 khz oscillator amplifier circuit 23 f3 stdby i/o c t 4ma x x input: hardware standby mode entry input active low. caution: external pull-up to v 33 required to select normal mode. output: standby mode active low output following software standby mode entry. note : in standby mode all pins are in high impedance except those marked active in stdby. 24 g4 rstin ic t x reset input 25 h5 v ssbkp s x stabilization for low power voltage regulator. 26 f4 v 18bkp sx stabilization for low power voltage regulator. requires external capacitors of at least 1f between v 18bkp and v ss18bkp . see figure 5 . note: if the low power voltage regulator is bypassed, this pin can be connected to an external 1.8v supply. 27 g5 v 18 s stabilization for main volt age regulator. requires external capacitors of at least 10f + 33nf between v 18 and v ss18 . see figure 5 . 28 h6 v ss18 s stabilization for main voltage regulator. 29 e4 v dda s supply voltage for a/d converter 30 g6 v ssa s ground voltage for a/d converter 31 f5 p1.0/t3.ocm pb/ain.0 i/o pu c t 4ma x x port 1.0 timer 3: output compare b adc: analog input 0 32 h7 p1.1/t3.icap a/t3.extclk /ain.1 i/o pu c t 4ma x x port 1.1 timer 3: input capture a or external clock input adc: analog input 1 33 h8 p1.2/t3.ocm pa/ain.2 i/o pu c t 4ma x x port 1.2 timer 3: output compare a adc: analog input 2 34 g8 p1.3/t3.icap b/ain.3 i/o pu c t 4ma x x port 1.3 timer 3: input capture b adc: analog input 3 35 f8 p1.4/t1.icap a/t1.extclk i/o pu c t 4ma x x port 1.4 timer 1: input capture a timer 1: external clock input table 6. str711/str712/str715 pin description pin n pin name type reset state 1) input output active in stdby main function (after reset) alternate function lqfp64 bga64 input level interrupt capability od pp
str71xf introduction 25/74 36 g7 p1.5/t1.icap b i/o pu c t 4ma x x port 1.5 timer 1: input capture b 37 f7 p1.6/t1.ocm pb i/o pu c t 4ma x x port 1.6 timer 1: output compare b 38 e8 v 33io-pll s supply voltage for digital i/o circuitry and for pll reference 2) 39 f6 v ssio-pll s ground voltage for digital i/o circuitry and for pll reference 2) 40 e7 p1.7/t1.ocm pa i/o pu c t 4ma x x port 1.7 timer 1: output compare a 41 d8 p1.8 i/o pd c t 4ma x x port 1.8 42 e6 p1.11/canrx i/o pu c t x4ma x x port 1.11 can: receive data input note: on str710 and str712 only 43 d7 p1.12/cantx i/o pu c t 4ma x x port 1.12 can: transmit data output note: on str710 and str712 only 42 e6 usbdp i/o c t usb bidirectional data ( data +). reset state = hiz note: on str710 and str711 only this pin requires an external pull-up to v 33 to maintain a high level. 43 d7 usbdn i/o c t usb bidirectional data (data -). reset state = hiz note: on str710 and str711 only. 44 c8 v ss s ground voltage for digital i/o circuitry 2) 45 e5 p1.9 i/o pd c t 4ma x x port 1.9 46 c7 p1.10/usbcl k i/o pd c/ t 4ma x x port 1.10 usb: 48 mhz clock input 47 d6 p1.13/hclk/i 0.scl i/o pd c t x4ma x x port 1.13 hdlc: reference clock input i2c clock 48 b8 p1.14/hrxd/i 0.sda i/o pu c t x4ma x x port 1.14 hdlc: receive data input i2c serial data 49 a8 p1.15/htxd i/o pu c t 4ma x x port 1.15 hdlc: transmit data output 50 a7 v ss s ground voltage for digital i/o circuitry 2) 51 a6 v 33 s supply voltage for digital i/o circuitry 2) table 6. str711/str712/str715 pin description pin n pin name type reset state 1) input output active in stdby main function (after reset) alternate function lqfp64 bga64 input level interrupt capability od pp
introduction str71xf 26/74 52 b7 p0.0/s0.miso /u3.tx i/o pu c t 4ma x x port 0.0 spi0 master in/slave out data uart3 transmit data output note: programming af function selects uart by default. bspi must be enabled by spi_en bit in the bootcr register. 53 b6 p0.1/s0.mosi /u3.rx i/o pu c t x4ma x x port 0.1 bspi0: master out/slave in data uart3: receive data input note: programming af function selects uart by default. bspi must be enabled by spi_en bit in the bootcr register. 54 a5 p0.2/s0.sclk /i1.scl i/o pu c t x4ma x x port 0.2 bspi0: serial clock i2c1: serial clock note: programming af function selects i2c by default. bspi must be enabled by spi_en bit in the bootcr register. 55 c6 p0.3/s0.ss /i1 .sda i/o pu c t 4ma x x port 0.3 spi0: slave select input active low. i2c1: serial data note: programming af function selects i2c by default. bspi must be enabled by spi_en bit in the bootcr register. 56 b5 p0.4/s1.miso i/o pu c t 4ma x x port 0.4 spi1: master in/slave out data 57 a4 v ss18 s stabilization for main voltage regulator. 58 c5 v 18 s stabilization for main volt age regulator. requires external capacitors of at least 10f + 33nf between v 18 and v ss18 . see figure 5 . 59 b4 v ss s ground voltage for digital i/os 60 a3 p0.5/s1.mosi i/o pu c t 4ma x x port 0.5 spi1: master out/slave in data 61 d5 p0.6/s1.sclk i/o pu c t x 4ma x x port 0.6 spi1: serial clock 62 b3 p0.7/s1.ss i/o pu c t 4ma x x port 0.7 spi1: slave select input active low table 6. str711/str712/str715 pin description pin n pin name type reset state 1) input output active in stdby main function (after reset) alternate function lqfp64 bga64 input level interrupt capability od pp
str71xf introduction 27/74 1. the reset configuration of the i/o ports is ipupd (input pull-up/pull down). refer to table 7 on page 28 . the port bit configuration at reset is pc0=1, pc1=1, pc2=0. the port data regist er bit (pd) value depends on the pu/pd column which specifies whether the pull-up or pull-down is enabled at reset 2. v 33io-pll and v 33 are internally connected. v ssio-pll and v ss are internally connected. 1.6 external connections figure 5. recommended external connection of v 18 and v 18bkp pins 63 c4 p0.8/u0.rx/u 0.tx i/o pd c t x4ma t port 0.8 uart0: receive data input uart0: transmit data output. note: this pin may be used for single wire uart (half duplex) if programmed as alternate function output. the pin will be tri-stated except when uart transmission is in progress 64 a2 p0.9/u0.tx/b oot.0 i/o pd c t 4ma x x port 0.9 select boot configuration input uart0: transmit data output table 6. str711/str712/str715 pin description pin n pin name type reset state 1) input output active in stdby main function (after reset) alternate function lqfp64 bga64 input level interrupt capability od pp lqfp144 lqfp64 58 57 27 129 128 33 nf 59 10 f 10 f 33 nf 54 55 1f 25 26 1f 28 58 v 18bkp v 18 v 18 v 18 v 18 v 18bkp
introduction str71xf 28/74 1.7 i/o port configuration legend: ain: analog input cmos: cmos input levels ipupd: input pull up /pull down ttl: ttl input levels n.a.: not applicable. in output mode, a read access to the port gets the output latch value. table 7. port bit configuration table configuration mode input buffer pxd register pxc2 register pxc1 register pxc0 register read access write access input ttl input floating ttl floating i/o pin don?t care 0 0 1 cmos input floating cmos floating i/o pin don?t care 0 1 0 cmos input pull-down (ipupd) cmos pull- down i/o pin 0 0 1 1 cmos input pull-up (ipupd) cmos pull-up i/o pin 1 0 1 1 analog input ain 0 don?t care 0 0 0 output output open-drain n.a. i/o pin 0 or 1 1 0 0 output push-pull n.a. last value written 0 or 1 1 0 1 alternate function open-drain cmos floating i/o pin don?t care 1 1 0 alternate function push-pull cm os floating i/o pin don?t care 1 1 1
str71xf introduction 29/74 1.8 memory mapping figure 6. memory map apb bridge 2 regs addressable memory space 0 1 2 3 4 4k 5 6 7 0x2000 0000 0x4000 0000 0x6000 0000 0x8000 0000 0xa000 0000 0xc000 0000 0xe000 0000 0xffff ffff 0xc000 0000 0xc000 1000 0xc000 2000 0xc000 3000 0xc000 4000 0xc000 5000 0xc000 6000 0xc000 7000 0xc000 8000 0xc000 9000 0xc000 a000 0xc000 b000 0xc000 c000 0xe000 1000 0xe000 2000 0xe000 3000 0xe000 4000 0xffff ffff 0x0000 0000 apb memory space 4 gbytes flash/ram/emi extmem 64mb 0xffff f800 4k eic 0xffff f800 apb bridge 1 regs reserved flash 256k+16k+36b b0f0 b0f4 b0f5 b0f6 b1f0 0x4000 0000 8k 8k 32k 64k 64k 64k flash memory space 272 kbytes + regs 0x4000 4000 0x4000 6000 0x4001 0000 0x4002 0000 0x4003 0000 reserved 4k (*) flash aliased at 0x0000 0000h by system decoder for booting with valid instruction upon reset from block b0 (8 kbytes) 0xe000 0000 0xe000 5000 0xe000 6000 0xe000 7000 0xe000 8000 0xe000 9000 0xe000 a000 0xe000 b000 i 2 c 0 i2c 1 reserved uart 0 uart 1 uart 2 uart 3 usb + ram bspi 0 bspi 1 xti reserved ioport 1 ioport 2 adc clkout timer 3 rtc wdg 0xe000 e000 0xe000 d000 0xe000 c000 0xc000 d000 0xc000 e000 prccu 1k can b0f7 0x400c 0000 0x400c 4000 0x4010 0000 reserved 8k timer 0 timer 1 timer 2 reserved reserved hdlc + ram reserved 0xc001 0000 0xc000 f000 b1f1 0x400c 2000 reserved 0x4004 0000 8k 0x4010 dfbf 36b flash registers 0x4000 2000 ram 64k apb1 apb2 eic b0f2 b0f1 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k reserved reserved ioport 0 64k 64k 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k b0f3 8k 8k 0x4000 8000 see figure 8
introduction str71xf 30/74 figure 7. mapping of flash memory versions b0f0 b0f4 reserved reserved b1f0 0x4000 0000 8k 8k 32k 64k 64k 64k flash memory space 64 kbytes + 16k rww + regs 0x4000 4000 0x4000 6000 0x4001 0000 0x4002 0000 0x4003 0000 reserved 0x400c 0000 0x400c 4000 0x4010 0000 reserved 8k b1f1 0x400c 2000 reserved 0x4004 0000 8k 0x4010 dfbf 36b flash registers 0x4000 2000 b0f2 b0f1 b0f3 8k 8k 0x4000 8000 b0f0 b0f4 b0f5 reserved b1f0 0x4000 0000 8k 8k 32k 64k 64k 64k flash memory space 128 kbytes + 16k rww + regs 0x4000 4000 0x4000 6000 0x4001 0000 0x4002 0000 0x4003 0000 reserved 0x400c 0000 0x400c 4000 0x4010 0000 reserved 8k b1f1 0x400c 2000 reserved 0x4004 0000 8k 0x4010 dfbf 36b flash registers 0x4000 2000 b0f2 b0f1 b0f3 8k 8k 0x4000 8000 b0f0 b0f4 b0f5 b0f6 b1f0 0x4000 0000 8k 8k 32k 64k 64k 64k flash memory space 256 kbytes + 16k rww + regs 0x4000 4000 0x4000 6000 0x4001 0000 0x4002 0000 0x4003 0000 b0f7 0x400c 0000 0x400c 4000 0x4010 0000 reserved 8k b1f1 0x400c 2000 reserved 0x4004 0000 8k 0x4010 dfbf 36b flash registers 0x4000 2000 b0f2 b0f1 b0f3 8k 8k 0x4000 8000 str715fr0xx str711fr0xx str712fr0xx str711fr1xx str712fr1xx str710f72xx str711fr2xx str712fr2xx str710fz1xx table 8. ram memory mapping part number ram size start address end address str715fr0xx str711fr0xx str712fr0xx 16 kbytes 0x2000 0000 0x2000 3fff str710fz1xx str711fr1xx str712fr1xx 32 kbytes 0x2000 0000 0x2000 7fff str710fr2xx str710rxx str711fr2xx str712fr2xx 64 kbytes 0x2000 0000 0x2000 ffff
str71xf introduction 31/74 figure 8. external memory map drawing not in scale addressable memory space 0 1 2 3 4 5 6 7 0x2000 0000 0x4000 0000 0x6000 0000 0x8000 0000 0xa000 0000 0xc000 0000 0xe000 0000 0xffff ffff 0x0000 0000 4 gbytes flash/ram/emi extmem 0xffff f800 reserved flash bcon3 bank3 bank2 0x6000 0000 16m 16m 16m 16m 0x6200 0000 0x6400 0000 0x6600 0000 reserved prccu bank1 ram apb1 apb2 eic bcon1 bcon2 bcon0 0x6c00 0000 0x6c00 0004 0x6c00 0008 0x6c00 000c register register register register bank0 external memory space 64 mbytes csn.0 csn.1 csn.2 csn.3 0x60ff ffff 0x62ff ffff 0x64ff ffff 0x66ff ffff
electrical parameters str71xf 32/74 2 electrical parameters 2.1 parameter conditions unless otherwise specified, all voltages are referred to v ss . 2.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a =25c and t a =t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 2.1.2 typical values unless otherwise specified, typical data are based on t a =25c, v 33 =3.3v (for the 3.0v v 33 3.6v voltage range) and v 18 =1.8v. they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ) . 2.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 2.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 9 . 2.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 10 . figure 9. pin loading conditions figure 10. pin input voltage l =50pf str7 pin v in str7 pin
str71xf electrical parameters 33/74 2.2 absolute maximum ratings stresses above those listed as ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 9. voltage characteristics symbol ratings min max unit v 33 - v ss external 3.3v supply voltage (including av dd and v 33io- pll ) 2) -0.3 4.0 v v 18bkp - v ssbkp digital 1.8v supply voltage on v 18bkp backup supply 2) -0.3 2.0 v in input voltage on true open drain pin (p0.10) 1) v ss -0.3 +5.5 input voltage on any other pin 1) v ss -0.3 v 33 +0.3 | ? v 33x | variations between different 3.3v power pins 50 50 mv | ? v 18x | variations between different 1.8v power pins 5) 25 25 |v ssx - v ss | variations between all the different ground pins 50 50 v esd(hbm) electro-static discharge voltage (human body model) see : absolute maximum ratings (electrical sensitivity) on page 47 v esd(mm) electro-static discharge voltage (machine model)
electrical parameters str71xf 34/74 notes : 1. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in >v 33 while a negative injection is induced by v in str71xf electrical parameters 35/74 2.3 operating conditions subject to general operating conditions for v 33 , and t a . 1. data guaranteed by characteri zation, not tested in production table 12. general operating conditions symbol parameter conditions min max unit f mclk internal cpu clock frequency accessing sram or external memory with 0 wait states 0 66 mhz accessing flash in burst mode 050 executing from flash with rww 0 45 1) accessing flash with 0 wait states 033 f pclk internal apb clock frequency 0 33 mhz v 33 standard operating voltage (includes v 33i0_pll) 3.0 3.6 v v 18bkp backup operating voltage 1.4 1.8 v t a ambient temperature range 6 partnumber suffix -40 85 c table 13. operating conditions at power-up / power-down symbol parameter conditions min typ max unit t v33 v 33 rise time rate subject to general operating conditions for t a . 20 s/v 20 ms/v
electrical parameters str71xf 36/74 2.3.1 supply current characteristics the current consumption is measured as described in figure 9 on page 32 and figure 10 on page 32 . total current consumption the mcu is placed under the following conditions: all i/o pins in input mode with a static value at v 33 or v ss (no load) all peripherals are disabled except if explicitly mentioned. embedded regulators are used to provide 1.8v (except if explicitly mentioned) subject to general operating conditions for v 33 , and t a . notes: 1. typical data are based on t a =25c, v 33 =3.3v. 2. data based on characterization results, tested in production at v 33 , f mclk max. and t a max. 3. based on device characterisa tion, device power consumption in stop mode at t a 25c is predicted to be 30a or less in 99.730020% of parts. 4. the conditions for these c onsumption measurements are des cribed in application note an2100. table 14. total current consumption symbol parameter conditions typ 1) max 2) unit i dd 4) supply current in run mode f mclk =66 mhz, ram execution 73.6 100 ma f mclk =32 mhz, flash non-burst execution 49.3 supply current in stop mode t a =25c 10 50 3) a supply current in standby mode osc32k bypassed 12 30 a
str71xf electrical parameters 37/74 table 15. typical power consumption data symbol parameter conditions typical current on v33 unit i ddrun run mode current from ram all periphs on mclk = 16 mhz, pclk = fclk = 16 mhz 23 ma mclk = 32 mhz, pclk = fclk = 32 mhz 40 mclk = 48 mhz, pclk = fclk = 24 mhz 50 mclk = 64 mhz, pclk = fclk = 32 mhz 63 all periphs off mclk = 16 mhz 16 mclk = 32 mhz 26 mclk = 48 mhz 39 mclk = 64 mhz 48 run mode current from flash all periphs on mclk = 16 mhz, pclk = fclk = 16 mhz 27 mclk = 32 mhz, pclk = fclk = 32 mhz 47 mclk = 48 mhz, pclk = fclk = 24 mhz 62 all periphs off mclk = 16 mhz 21 mclk = 32 mhz 36 mclk = 48 mhz 53 i ddslow slow mode current mclk = ck_af (32 khz), mvr off 1.7 i ddwait wait mode current (all periphs on) pclk = fclk = 1 mhz 13 i ddlpwait lpwait mode current ck_af (32 khz), main vreg off, flash in power-down 37 a i ddstop stop mode current main vreg off, flash in power down, rtc on 18 main vreg off, flash in power down, rtc off 10 i ddsb standby mode current lp vreg on, lvd on, rtc on 10 lp vreg off (ext 1.8v on v18bkp), lvd on, rtc on 9 lp vreg off (ext1.8v on v18bkp), lvd off, rtc on 5 lp vreg off (ext 1.8v on v18bkp), lvd off, rtc off 1
electrical parameters str71xf 38/74 figure 11. stop i dd vs. v 33 figure 12. standby i dd vs. v 33 figure 13. wfi i dd vs. v 33 0 10 20 30 40 50 60 70 80 90 100 3 3.1 3.2 3.3 3.4 3.5 3.6 v33 (v) iddstop (a) ta=-45 to +25c ta=+90c 0 5 10 15 20 25 3 3.1 3.2 3.3 3.4 3.5 3.6 v33 (v) iddstdby (a) ta=-45c ta=0c ta=+25c ta=+90c 50 60 70 80 90 100 3 3.1 3.2 3.3 3.4 3.5 3.6 v33 (v) iddwfi (a) ta=-40 to +90c
str71xf electrical parameters 39/74 on-chip peripherals notes : 1. data based on a differential i dd measurement between reset configur ation and timer counter running at 16mhz. no ic/oc programm ed (no i/o pads toggling). 2. data based on a differential i dd measurement between the on-chip peripheral when kept under reset and not clocked and the on-chip peripheral when clocke d and not kept under reset. no i/o pads toggling. 3. data based on a differential i dd measurement between reset configuration and continuous a/d conversions. table 16. peripheral current consumption symbol parameter conditions typ unit i dd(pll1) pll1 supply current t a = 25c 3.42 ma i dd(pll2) pll2 supply current 5.81 i dd(tim) tim timer supply current 1) t a = 25c, f pclk =33 mhz 0.88 i dd(bspi) bspi supply current 2) 1.1 i dd(uart) uart supply current 2) 1.05 i dd(i2c) i2c supply current 2) 0.45 i dd(adc) adc supply current when converting 5) 1.89 i dd(hdlc) hdlc supply current 2) 1.82 i dd(usb) usb supply current 2) 2.08 i dd(can) can supply current 2) 1.11
electrical parameters str71xf 40/74 2.3.2 clock and timi ng characteristics external clock sources subject to general operating conditions for v 33 , and t a . notes: 1. data based on design simulation and/or technology characteristics, not tested in production. figure 14. ck external clock source table 17. ck external clock characteristics symbol parameter conditions min typ max unit f ck external clock source frequency 0 16.5 mhz v ckh ck input pin high level voltage 0.7xv 33 v 33 v v ckl ck input pin low level voltage v ss 0.3xv 33 t w(ck) t w(ck) ck high or low time 1) 25 ns t r(ck) t f(ck) ck rise or fall time 1) 5 i l ck input leakage current v ss v in v 33 1 a ck f clk external str710 clock source v ckl v ckh t r(ck) t f(ck) t w(ckh) t w(ckl) i l 90% 10% t ck
str71xf electrical parameters 41/74 notes: 1. data based on design simulation and/or technology characteristics, not tested in production. table 18. rtcxt1 external clock characteristics symbol parameter conditions min typ max unit f rtcxt1 external clock source frequency 0 500 khz v rtcxt1h rtcxt1 input pin high level voltage 0.7xv 33 v 33 v v rtcxt1l rtcxt1 input pin low level voltage v ss 0.3xv 33 t w(rtcxt1) t w(rtcxt1) rtcxt1 high or low time 1) 100 ns t r(rtcxt1) t f(rtcxt1) rtcxt1 rise or fall time 1) 5 i l rtcxt1 input leakage current v ss v in v 33 1 a
electrical parameters str71xf 42/74 osc32k crystal / ceramic resonator oscillator the str7 rtc clock can be supplied with a 32khz crystal/ceramic resonator oscillators. all the information given in this paragraph are based on characterization results with specified typical external components. in the application, the resonator and the load capacitors have to be placed as close as possibl e to the oscillator pins in order to minimize output distortion and start-up st abilization time. refer to the cr ystal resonator manufacturer for more details (frequency, package, accuracy...). notes: 1. the oscillator selection can be optimized in terms of supply current using an hi gh quality resonator with small r s value for example msiv-tin32.768khz. refer to crystal manufacturer for more details 2. t su(osc32khz) is the start-up time measured from the mome nt it is enabled (by software) to a stabilized 32khz oscillation is reached. this value is measured for a standard crystal resonator and it can vary significantly with t he crystal manufacturer figure 15. typical application with a 32khz crystal table 19. 32k oscillator characteristics (f osc32k= 32.768khz) symbol parameter conditions typ unit r f feedback resistor 2.7 m ? c l1 c l2 recommended load capacitance versus equivalent serial resistance of the crystal (r s ) 1) r s =40k ? 12.5 pf i 2 rtcxt2 driving current v 33 =3.3v v in =v ss 3.2 a g m oscillator transconductance 8 a/v t su(osc32khz) 2) startup time v 33 is stabilized 3s rtcxt2 rtcxt1 f osc32k c l1 c l2 i 2 r f str710 32khz when resonator with integrated capacitors resonator feedback loop
str71xf electrical parameters 43/74 figure 16. rtc crystal oscillator and resonator pll electrical characteristics v 33 = 3.0 to 3.6v, v 33iopll = 3.0 to 3.6v, t a = -40 / 85 c unless otherwise specified. c l c l rtcxti rtcxto r s rtcxti rtcxto device device table 20. pll1 characteristics symbol parameter test conditions value unit min typ max f pllclk1 pll multiplier output clock f pll1 x 24 165 mhz f pll1 pll input clock fref_range = 0 1.5 3.0 mhz fref_range = 1 mx[1:0]=?00? or ?01? 3.0 8.25 mhz fref_range = 1 mx[1:0]=?10? or ?11? 3.0 6 mhz pll input clock duty cycle 25 75 % f free1 pll free running frequency fref_range = 0 mx[1:0]=?01? or ?11? 125 khz fref_range = 0 mx[1:0]=?00? or ?10? 250 khz fref_range = 1 mx[1:0]=?01? or ?11? 250 khz fref_range = 1 mx[1:0]=?00? or ?10? 500 khz t lock1 pll lock time fref_range = 0 stable input clock stable v 33iopll , v 18 300 s fref_range = 1 stable input clock stable v 33iopll , v 18 600 s ? t jitter1 pll jitter (peak to peak) t pll = 4 mhz, mx[1:0]=?11? global output division = 32 (output clock = 2 mhz) 0.7 2 ns
electrical parameters str71xf 44/74 table 21. pll2 characteristics symbol parameter test conditions value unit min typ max f pllclk2 pll multiplier output clock f pll x 28 140 mhz f pll2 pll input clock fref_range = 0 1.5 3.0 mhz fref_range = 1 3.0 5 mhz t lock2 pll lock time fref_range = 0 stable input clock stable v 33iopll , v 18 300 s fref_range = 1 stable input clock stable v 33iopll , v 18 600 s ? t jitter2 pll jitter (peak to peak) t pll = 4 mhz, mx[1:0]=?11? global output division = 32 (output clock = 2 mhz) 0.7 2 ns table 22. low-power mode wake-up timing symbol parameter typ unit t wulpwfi wake-up from lpwfi mode 26 s t wustop wake-up from stop mode 131 s t wustby wake-up from standby mode 2 s
str71xf electrical parameters 45/74 2.3.3 memory characteristics flash memory v 33 = 3.0 to 3.6v, t a = -40 to 85 c unless otherwise specified. notes: 1. t a =85c after 0 cycles. guaranteed by ch aracterization, not tested in production. 2. guaranteed by design, not tested in production 2.3.4 emc characteristics susceptibility tests ar e performed on a sample basis du ring product characterization. table 23. flash memory characteristics symbol parameter test conditions value unit min. typ max 1) t pw word program 40 s t pdw double word program 60 s t pb0 bank 0 program (256k) double word program 1.6 2.1 s t pb1 bank 1 program (16k) double word program 130 170 ms t es sector erase (64k) not preprogrammed preprogrammed 2.3 1.9 4.0 3.3 s t es sector erase (8k) not preprogrammed preprogrammed 0.7 0.6 1.1 1.0 s t es bank 0 erase (256k) not preprogrammed preprogrammed 8.0 6.6 13.7 11.2 s t es bank 1 erase (16k) not preprogrammed preprogrammed 0.9 0.8 1.5 1.3 s t rpd 2) recovery when disabled 20 s t psl 2) program suspend latency 10 s t esl 2) erase suspend latency 300 s n end_b0 endurance (bank 0 sectors) 10 kcycles n end_b1 endurance (bank 1 sectors) 100 kcycles t ret data retention (bank 0 and bank 1) t a =55 20 years t esr erase suspend rate min time from erase resume to next erase suspend 20 ms
electrical parameters str71xf 46/74 functional ems (electro magnetic susceptibility) based on a simple running application on the product (toggling 2 leds through i/o ports), the product is stressed by two electro magnetic ev ents until a failure occurs (indicated by the leds). esd : electro-static discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 1000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100pf capacitor, until a functional disturbance occurs. this test conforms with the iec 1000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in the table below based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations: the software flowchart must include the management of runaway conditions such as: corrupted program counter unexpected reset critical data corruption (control registers...) prequalification trials: most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the reset pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). in the case of an arm7 cpu, in order to write robust code that can withstand all kinds of stress, such as very strong electromagnetic disturbance, it is mandatory that the data abort, prefetch abort and undefined instruction exceptions are managed by the application software. this will prevent the code going in to an undefined stat e or performing any unexpected operation.
str71xf electrical parameters 47/74 electro magnetic interference (emi) based on a simple application running on the product (toggling 2 leds through the i/o ports), the product is monitored in terms of emi ssion. this emission test is in line with the norm sae j 1752/3 which sp ecifies the boar d and the loading of each pin. notes : 1. not tested in production. 2. bga and lqfp devices have similar emi characteristics. absolute maximum ratings (electrical sensitivity) based on three different tests (esd, lu and dlu) using specific measurement methods, the product is stressed in order to determine its per formance in terms of electrical sensitivity. for more details, refer to the application note an1181. electro-static discharge (esd) electro-static discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). two models can be simulated: human body model and machine model. this test conforms to the jesd22-a114a/a115a standard. table 24. ems data symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v 33 = 3.3v, t a = +25c, f mclk = 32mhz conforms to iec 1000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100pf on v dd and v ss pins to induce a functional disturbance v 33 = 3.3v, t a = +25c, f mclk = 32mhz conforms to iec 1000-4-4 4a table 25. emi data symbol parameter conditions monitored frequency band max vs. [f osc4m /f hclk ] unit 16/ 48mhz 16/8mhz s emi peak level v 33 = 3.3v, t a = +25c, lqfp64 package conforming to sae j 1752/3 0.1mhz to 30 mhz 17 19 db v 30 mhz to 130 mhz 17 16 130 mhz to 1ghz 11 11 sae emi level 4 3 -
electrical parameters str71xf 48/74 notes: 1. data based on characterization results, not tested in production. static and dynamic latch-up lu : 3 complementary static tests are required on 10 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable i/o pin) are performed on each sample. this test conforms to the eia/jesd 78 ic latch-up standard. for more details, refer to the application note an1181. dlu : electro-static discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the mi cro and the component is put in reset mode. this test conforms to the iec1000-4-2 and saej1752/3 standards. for more details, refer to the application note an1181. electrical sensitivities notes: 1. class description: a class is an stmi croelectronics internal specification. all its limits are higher than the jedec specifications, that means when a device belongs to class a it exceeds the jedec standard. b class strictly covers all the jede c criteria (international standard). table 26. esd absolute maximum ratings symbol ratings conditions maximum value 1) unit v esd(hbm) electro-static discharge voltage (human body model) t a = +25c 2000 v v esd(mm) electro-static discharge voltage (machine model) 200 v esd(cdm) electro-static discharge voltage (charge device model) 750 on corner pins, 500 on others symbol parameter conditions class 1) lu static latch-up class t a = +25c t a = +85c t a = +105c a a a dlu dynamic latch-up class v dd = 3.3v, f osc4m = 4mhz, f mclk = 32mhz, t a = +25c a
str71xf electrical parameters 49/74 2.3.5 i/o port pin characteristics general characteristics subject to general operating conditions for v 33 and t a unless otherwise specified. all unused pins must be kept at a fixed voltage: using the output mode of the i/o for example or an external pull-up or pull-down resistor. notes : 1. data based on characterization results, not tested in production. 2. hysteresis voltage between schmitt trigger switching levels. based on c haracterization results, not tested. 3. when the current limitation is not possible, the v in absolute maximum rating must be respected, otherwise refer to i inj(pin) specification. a positive injection is induced by v in >v 33 while a negative injection is induced by v in electrical parameters str71xf 50/74 figure 17. r pu vs. v 33 with v in =v ss figure 18. i pu vs. v 33 with v in =v ss -250.0 -200.0 -150.0 -100.0 -50.0 0.0 3 3.1 3.2 3.3 3.4 3.5 3.6 v33 (v) rpu (kohm) ta=-45c ta=0c ta=+25c ta=+90c -30 -25 -20 -15 -10 -5 0 3 3.1 3.2 3.3 3.4 3.5 3.6 v33 (v) ipu (a) ta=-45c ta=0c ta=+25c ta=+90c figure 19. r pd vs. v 33 with v in =v 33 figure 20. i pd vs. v 33 with v in =v 33 0.0 50.0 100.0 150.0 200.0 250.0 300.0 3 3.1 3.2 3.3 3.4 3.5 3.6 v33 (v) rpd (kohm) ta=-45c ta=0c ta=+25c ta=+90c 0 5 10 15 20 25 30 3 3.1 3.2 3.3 3.4 3.5 3.6 v33 (v) ipd (a) ta=-45c ta=0c ta=+25c ta=+90c
str71xf electrical parameters 51/74 output driving current subject to general operating conditions for v 33 and t a unless otherwise specified. notes: 1. the i io current sunk must always respect the absolute maximum rating specified in table 10 and the sum of i io (i/o ports and control pins) must not exceed i vss . 2. the i io current sourced must always respect the absolute maximum rating specified in table 10 and the sum of i io (i/o ports and control pins) must not exceed i v33 . table 28. output driving current i/o type symbol parameter conditions min max unit standard v ol 1) output low level voltage for an i/o pin when 8 pins are sunk at same time (see figure 21 ) i io =+4ma 0.4 v v oh 2) output high level voltage for an i/o pin when 4 pins are sourced at same time (see figure 21 and figure 23 ) i io =-4ma v 33 -0.8 high current v ol 1) output low level voltage for an i/o pin when 8 pins are sunk at same time (see figure 21 ) i io =+8ma 0.4 v oh 2) output high level voltage for an i/o pin when 4 pins are sourced at same time (see figure 21 and figure 23 ) i io =-8ma v 33 -0.8
electrical parameters str71xf 52/74 figure 21. typical v ol and v oh at v 33 =3.3v (high current ports) 3.01 3.02 3.03 3.04 3.05 3.06 3.07 3.08 3.09 -4 -8 iio(ma) voh(v) ta=-45c ta=0c ta=+25c ta=+90c 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 -4 -8 iol (ma) vol(v) ta=-45c ta=0c ta=+25c ta=+90c
str71xf electrical parameters 53/74 figure 22. typical v ol vs. v 33 figure 23. typical v oh vs. v 33 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 3 3.1 3.2 3.3 3.4 3.5 3.6 v33 (v) vol (v) iio=4ma ta=-45c ta=0c ta=+25c ta=+90c 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 3 3.1 3.2 3.3 3.4 3.5 3.6 v33 (v) vol(v) iio=8ma ta=-45c ta=0c ta=+25c ta=+90c 2.00 2.20 2.40 2.60 2.80 3.00 3.20 3.40 3.60 3 3.1 3.2 3.3 3.4 3.5 3.6 v33 (v) voh (v) iio=4ma ta=-45c ta=0c ta=+25c ta=+90c 2.00 2.20 2.40 2.60 2.80 3.00 3.20 3.40 3.60 3 3.1 3.2 3.3 3.4 3.5 3.6 v33 (v) voh(v) iio=8ma ta=-45c ta=0c ta=+25c ta=+90c
electrical parameters str71xf 54/74 rstin pin the rstin pin input driver is cmos. a permanent pu ll-up is present which is the same as as r pu (see table 27 on page 49 ) subject to general operating conditions for v 33 and t a unless otherwise specified. notes: 1. data based on characterization results, not tested in production. 2) data guaranteed by design, not tested in production. figure 24. recommended rstin pin protection . 1) notes: 1. the r pu pull-up equivalent resistor is based on a resistive transistor (corresponding i pu current characteristics described in figure 18 ). 2. the reset network protects t he device against par asitic resets. 3. the user must ensure that the level on the rstin pin can go below the v il(rstinn) max. level specified in table 29 . otherwise the reset will not be taken into account internally. 2.3.6 tim timer characteristics subject to general operating conditions for v 33 , f mclk , and t a unless otherwise specified. refer to section 2.3.5: i/o port pin characteristics on page 49 for more details on the input/output alternate function characteristics (output compare, input capture, external clock, pwm output...). table 29. reset pin characteristics symbol parameter conditions min typ 1) max unit v il(rstinn) rstin input low level voltage 1) 0.8 v v ih(rstinn) rstin input high level voltage 1) 2 v f(rstinn) rstin input filtered pulse 2) 500 ns v nf(rstinn) rstin input not filtered pulse 2) 1.2 s 0.01 f v 33 0.01 f external reset circuit 4.7k ? required recommended str7x filter r pu v 33 internal reset v 33 rstin table 30. tim characteristics symbol parameter conditions min typ max unit t w(icap)in input capture pulse time 2 t ck_tim
str71xf electrical parameters 55/74 2.3.7 emi - memory interface subject to general operating conditions for v dd , f hclk , and t a unless otherwise specified. the tables below use a variable which is derived from the emi_bconn registers (described in the str71x reference manual) and represents the special characteristics of the programmed memory cycle. t res(tim) timer resolution time 1 t pclk2 f pclk2 = 30mhz 33.3 ns f ext timer external clock frequency f ck_tim(max) = f mclk 0 f ck_tim /4 mhz f ck_tim = f mclk = 60mhz 015mhz res tim timer resolution 16 bit t counter 16-bit counter clock period when internal clock is selected 1 65536 t pclk f pclk2 = 30mhz 0.033 2184 s t max_count maximum possible count 65536x 65536 t pclk f pclk2 = 30mhz 143.1 s table 30. tim characteristics symbol parameter conditions min typ max unit table 31. emi general characteristics symbol parameter value t mclk cpu clock period 1 / f mclk t c memory cycle time wait states t mclk x (1 + [c_length])
electrical parameters str71xf 56/74 see figure 25 , figure 26 , figure 27 and figure 28 for related timing diagrams. 1. data based on characterisation results, not tested in production. see figure 29 , figure 30 , figure 31 and figure 32 for related timing diagrams. 1. data based on characterisation results, not tested in production. table 32. emi read operation symbol parameter test conditions value unit min 1) typ max 1) t rcr read to csn removal time mclk=50 mhz 4 wait states 50 pf load on all pins 19 t mclk 21 ns t rp read pulse time 98 t c 100 ns t rds read data setup time 22 ns t rdh read data hold time 0 ns t ras read address setup time 27 1.5*t m clk 33 ns t rah read address hold time 0.65 2 ns t rat read address turnaround time 1.9 3.25 ns t rrt rdn turnaround time 20 t mclk 21 ns table 33. emi write operation symbol parameter test conditions value unit min 1) typ max 1) t wcr wen to csn removal time mclk=50 mhz 3 wait states 50 pf load on all pins 20 t mclk 22.5 ns t wp write pulse time 77.5 t c 80 ns t wds1 write data setup time 1 97 t c + t mclk 100 ns t wds2 write data setup time 2 77 t c 80 ns t wdh write data hold time 20 t mclk 23 ns t was write address setup time 27 1.5*t mclk 33 ns t wah write address hold time 0.6 3 ns t wat write address turnaround time 1.75 4.1 ns t wwt wen turnaround time 20 t mclk 23 ns
str71xf electrical parameters 57/74 figure 25. read cycle timing: 16-bit read on 16-bit memory figure 26. read cycle timing: 32-bit read on 16-bit memory see ta bl e 3 2 for read timing data. figure 27. read cycle timing: 16-bit read on 8-bit memory csn.x wen.x a[23:0] d[15:0] rdn (input) address data input t rds t rdh t rcr t ras t rah t rp csn.x wen.x a[23:0] d[15:0] rdn (input) address data input t rds t rdh t rcr t ras t rah data input t rds t rdh t rrt t rah address t rat t rp t rp csn.x wen.x a[23:0] d[7:0] rdn (input) address data input t rds t rdh t rcr t ras t rah data input t rds t rdh t rrt t rah address t rat t rp t rp
electrical parameters str71xf 58/74 figure 28. read cycle timing: 32-bit read on 8-bit memory see ta bl e 3 2 for read timing data. figure 29. write cycle timing: 16-bit write on 16-bit memory figure 30. write cycle timing: 32-bit write on 16-bit memory see ta b l e 4 1 for write timing data. csn.x wen.x a[23:0] d[7:0] rdn (input) address data input t rds t rdh t rcr t ras t rah data input t rds t rdh t rrt t rah address t rat t rp t rp t rrt t rah address t rat t rp data input t rds t rdh t rrt t rah address t rat t rp data input t rds t rdh csn.x wen.x a[23:0] d[15:0] rdn (output) address data output t wdh t wcr t was t wds1 t wah t wp csn.x wen.x a[23:0] d[15:0] rdn (output) address data output t wds1 t wdh t wcr t was t wah t wp data output t wds2 t wdh t wwt t wah address t wat t wp
str71xf electrical parameters 59/74 figure 31. write cycle timing: 16-bit write on 8-bit memory figure 32. write cycle timing: 32-bit write on 8-bit memory see ta bl e 3 3 for write timing data. csn.x wen.x a[23:0] d[7:0] rdn (output) address data output t wds1 t wdh t wcr t was t wah t wp data output t wds2 t wdh t wwt t wah address t wat t wp csn.x wen.x a[23:0] d[7:0] rdn (output) address data output t wds1 t wdh t wcr t was t wah t wp data output t wds2 t wdh t wwt t wah address t wat t wp t wwt t wah address t wat t wp data output t wds2 t wdh t wwt t wah address t wat t wp data output t wds2 t wdh
electrical parameters str71xf 60/74 2.3.8 communications interfaces i 2 c - inter ic control interface subject to general operating conditions for v 33 , f pclk1 , and t a unless otherwise specified. the str7 i 2 c interface meets the requirements of the standard i 2 c communication protocol described in the following table with the restriction mentioned below: note: restriction: the i/o pins which sda and scl are mapped to are not ?true? open-drain: when configured as open-drain, the pmos connected between the i/o pin and v 33 is disabled, but it is still present. also , there is a protec tion diode between the i/o pin and v 33 . consequently, when using this i 2 c in a multi-master network, it is not possible to power off the str7x while some another i 2 c master node remains powered on: otherwise, the str7x will be powered by the protection diode. refer to i/o port characteristics for more details on the input/output alternate function characteristics (sda and scl). notes: 1. data based on standard i 2 c protocol requirement, not tested in production. 2. the device must internally provide a hold time of at least 300ns for th e sda signal in order to bridge the undefined region of the falling edge of scl. 3. the maximum hold time of the star t condition has only to be met if the interface does not stretch the low table 34. i2c characteristics symbol parameter standard mode i 2 c fast mode i 2 c 5) unit min 1) max 1) min 1) max 1) t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0 3) 0 2) 900 3) t r(sda) t r(scl) sda and scl rise time 1000 20+0.1c b 300 t f(sda) t f(scl) sda and scl fall time 300 20+0.1c b 300 t h(sta) start condition hold time 4.0 0.6 s t su(sta) repeated start condition setup time 4.7 0.6 t su(sto) stop condition setup time 4.0 0.6 s t w(sto:sta) stop to start condition time (bus free) 4.7 1.3 s c b capacitive load for each bus line 400 400 pf
str71xf electrical parameters 61/74 period of scl signal. 4. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . 5. f pclk1 , must be at least 8mhz to achieve max fast i 2 c speed (400khz). 6. the following table gives the values to be wri tten in the i2cccr register to obtain the required i 2 c scl line frequency. figure 33. typical application with i 2 c bus and timing diagram 4) legend: r p = external pull-up resistance f scl = i 2 c speed na = not achievable note: for speeds around 200 khz, achieved speed can have 5% tolerance for other speed ranges, achieved speed can have 2% tolerance the above variations depend on the accuracy of the external components used. usb characteristics the usb interface is usb-if certified (low speed and full speed). table 35. scl frequency table ( f pclk1 =8 mhz.,v 33 = 3.3 v) f scl (khz) i2cccr value r p =4.7k ? 400 83 300 85h 200 8ah 100 24h 50 4ch 20 c4h repeated start start stop start t f(sda) t r(sda) t su(sda) t h(sda) t f(sck) t r(sck) t w(sckl) t w(sckh) t h(sta) t su(sto) t su(sta) t w(sto:sta) sda scl 4.7k ? sda str7 scl v dd 100 ? 100 ? v dd 4.7k ? i 2 cbus
electrical parameters str71xf 62/74 2.3.9 adc characteristics subject to general operating conditions for av dd , f pclk2 , and t a unless otherwise specified. notes: 1. unless otherwise specifi ed, typical data are based on t a =25c and av dd -av ss =3.3v. they are given only as design guidelines and are not tested. 2. any added external serial resistor will downgrade the adc accuracy (especially for resistance greater than 10k ? ). data based on characterization results, not tested in production. 3. calibration is needed once after each power-up. table 36. adc characteristics symbol parameter conditions min typ 1) max unit f mod modulator oversampling frequency 2.1 mhz v ain conversion voltage range 2)3) 02.5v i lkg negative input leakage current on analog pins v in < v ss, | i in |< 400a on adjacent analog pin 56 a pbr passband ripple 0.1 db sinad s/n and distortion 56 63 db thd total harmonic distortion 60 74 db z in input impedance f mod = 2 mhz 1 m ? c adc internal sample and hold capacitor 3.2 pf t conv total conversion time (including sampling time) 4096/ f mod (max) i adc normal mode t a = 27 c 2.5 3.0 ma standby mode t a = 27 c 1 a
str71xf electrical parameters 63/74 1. data based on characterisation, not tested in production. adc accuracy vs. negative injection current: in jecting negative current on any of the standard (non- robust) analog input pins should be av oided as this significantly reduce s the accuracy of the conversion being performed on another analog input. it is recommend ed to add a schottky diode (pin to ground) to standard analog pins which may potentia lly inject negative current. the effect of negative injection current on robust pins is specified in section 2.3.5 . any positive injection current with in the limits specified for i inj(pin) and i inj(pin) in section 2.3.5 does not affect the adc accuracy. table 37. adc accuracy with f pclk2 = 20mhz, f adc =10mhz, av dd =3.3v symbol parameter conditions min typ max unit adc_data(0v) converted code when ain=0v 1) 2370 2565 dec- imal code adc_data(2.5v) converted code when ain=2.5v 1) 1480 1680 vcm center voltage of sigma-delta modulator 1) 1.23 1.25 1.30 v tue total unadjusted error in this type of adc, calibration is necessary to correct gain error and offset errors. once calibrated, the tue is limited to the ile. |e d | differential linearity error 1) 1.96 2.19 lsb |e l | integral linearity error 1) 2.36 3.95
electrical parameters str71xf 64/74 figure 34. adc accura cy characteristics analog power supply and reference pins the av dd and av ss pins are the analog power supply of the a/d converter cell. they act as the high and low reference voltages for the conversion. separation of the digital and analog power pins allow board designers to improve a/d performance. conversion accuracy can be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines (see : general pcb design guidelines ). general pcb design guidelines to obtain best results, some general design and layout rules should be followed when designing the application pcb to shield the noise-sensitive, analog physical interface from noise-generating cmos logic signals. use separate digital and analog planes. the analog ground plane should be connected to the digital ground plane via a single point on the pcb. filter power to the analog power planes. it is recommended to connect capacitors, with good high frequency characteristics, between the power and ground lines, placing 1lsb ideal 1lsb ideal avdd avss ? 4095 ----------------------------------------------- - = v ain (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. digital result adc_data register 4095 4094 4093 5 4 3 2 1 0 123 4093 4094 4095 (1) (2) e d e l (3) av dd av ss adc_data(0v) adc_data(2.5v) vcm 3100 3101 3102 3103 out of range 1633
str71xf electrical parameters 65/74 0.1f and optionally, if needed 10pf capacitors as close as possible to the str7 power supply pins and a 1 to 10f capacitor close to the power source (see figure 35 ). the analog and digital power supplies should be connected in a star network. do not use a resistor, as av dd is used as a reference voltage by the a/d converter and any resistance would cause a voltage drop and a loss of accuracy. properly place components and route the signal traces on the pcb to shield the analog inputs. analog signals paths should run over the analog ground plane and be as short as possible. isolate analog signals from digital signals that may switch while the analog inputs are being sampled by the a/d converter. do not toggle digital outputs near the a/d input being converted. software filtering of spurious conversion results for emc performance reasons, it is recommended to filter a/d conversion outliers using software filtering techniques. figure 35. power supply filtering v ss v 33 0.1 f v 33 str710 av dd av ss power supply source str7 digital noise filtering external noise filtering 1 to 10 f 0.1 f (3.3v)
package characteristics str71xf 66/74 3 package characteristics 3.1 package mechanical data figure 36. 64-pin low profile quad flat package (10x10) 1 dim. mm inches min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.007 0.009 0.011 c 0.09 0.20 0.004 0.008 d 12.00 0.472 d1 10.00 0.394 e 12.00 0.472 e1 10.00 0.394 e 0.50 0.020 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n 64 a a2 a1 c h l1 l e e1 d d1 e b recommended footprint (dimensions in mm)
str71xf package characteristics 67/74 figure 37. 144-pin low profile quad flat package dim. mm inches (1) 1.values in inches are converted from mm and rounded to 3 decimal digits. min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.057 b 0.17 0.22 0.27 0.007 0.011 c 0.09 0.20 0.004 0.008 d 21.80 22.00 22.20 0.858 0.867 0.874 d1 19.80 20.00 20.20 0.780 0.787 0.795 d3 17.50 0.689 e 21.80 22.00 22.20 0.858 0.867 0.874 e1 19.80 20.00 20.20 0.780 0.787 0.795 e3 17.50 0.689 e 0.50 0.020 k 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n 144 jedec ref. ms-026-bfb a a2 a1 b c 36 37 72 73 108 109 144 e1 e d1 d 1 h b l l1 seating plane 0.08 mm .003 in. e e3 d3 recommended footprint (dimensions in mm)
package characteristics str71xf 68/74 figure 38. 64-low profile fine pitch ball grid array package figure 39. 144-low profile fine pitch ball grid array package dim. mm inches min typ max min typ max a 1.210 1.700 0.048 0.067 a1 0.270 0.011 a2 1.120 0.044 b 0.450 0.500 0.550 0.018 0.020 0.022 d 7.750 8.000 8.150 0.305 0.315 0.321 d1 5.600 0.220 e 7.750 8.000 8.150 0.305 0.315 0.321 e1 5.600 0.220 e 0.720 0.800 0.880 0.028 0.031 0.035 f 1.050 1.200 1.350 0.041 0.047 0.053 ddd 0.120 0.005 number of pins n 64 dim. mm inches min typ max min typ max a 1.21 1.70 0.048 0.067 a1 0.21 0.008 a2 1.12 0.044 b 0.35 0.40 0.45 0.014 0.016 0.018 d 9.85 10.00 10.15 0.388 0.394 0.400 d1 8.80 0.346 e 9.85 10.00 10.15 0.388 0.394 0.400 e1 8.80 0.346 e 0.80 0.031 f 0.60 0.024 ddd 0.10 0.004 eee 0.15 0.006 fff 0.08 0.003 number of pins n 144
str71xf package characteristics 69/74 3.2 thermal characteristics the average chip-junction temperature, t j , in degrees celsius, may be calculated using the following equation: t j = t a + (p d x ja ) (1) where: t a is the ambient temperature in c, ja is the package junction-to-ambient thermal resistance, in c/w, p d is the sum of p int and p i/o (p d = p int + p i/o ), p int is the product of i dd and v dd , expressed in watts. this is the chip internal power. p i/o represents the power dissipation on input and output pins; most of the time for the application p i/o < p int and can be neglected. on the other hand, p i/o may be significant if the device is configured to drive continuously external modules and/or memories. an approximate relationship between p d and t j (if p i/o is neglected) is given by: p d = k / (t j + 273c) (2) therefore (solving equations 1 and 2): k = p d x (t a + 273c) + ja x p d 2 (3) where: k is a constant for the particular part, which may be determined from equation (3) by measuring p d (at equilibrium) for a known t a. using this value of k, the values of p d and t j may be obtained by solving equations (1) and (2) iteratively for any value of t a . table 38. thermal characteristics symbol parameter value unit ja thermal resistance junction-ambient lqfp 144 - 20 x 20 mm / 0.5 mm pitch 42 c/w ja thermal resistance junction-ambient lqfp 64 - 10 x 10 mm / 0.5 mm pitch 45 c/w ja thermal resistance junction-ambient lfbga 64 - 8 x 8 x 1.7mm 58 c/w ja thermal resistance junction-ambient lfbga 144 - 10 x 10 x 1.7mm 50 c/w
product history str71xf 70/74 4 product history there are two versions of the str710f series products. the two versions are functionally identical and differ only with the points listed below. version "a" was the first version produced and delivered. the second version, version "z", is currently being ph ased into production an d will replace version "a". version "z" has lower power consumption in stop mode. marking the difference between the two versions is visi ble on the marking of the product, with the version letter on top of the part number. this version letter is visible in figure 40 shows a tqfp144 "a" str710 and a tqfp64 "z" str712 figure 40. version marking table 39. a and z version differences feature a version z version arm7tdmi core device identification (id) c ode register (see arm7tdmi technical reference manual) version bits [31:28] = 0001 version bits [31:28] = 0010 low power mode consumption in stop mode at 25 c not guaranteed typical 49 a 50 a maximum at 25c. less than 30 a at 25 c for 99.730020% of parts str710fz2t6 2208jvg mlt225571 str712fr2 2208jvg mlt225571 t6 z a
str71xf order codes 71/74 5 order codes table 40. order codes partnumber flash kbytes ram kbyte s emi usb can i/o ports package temp. range str710fz1t6 128+16 32 yes yes yes 48 lqfp144 20 x 20 -40 to +85c str710fz2t6 256+16 64 str710rzt6 0 64 str710fz1h6 128+16 32 ye s ye s ye s 4 8 lfbga144 10 x 10 1.7 str710fz2h6 256+16 64 str710rzh6 0 64 str711fr0h6 64+16 16 no ye s n o 3 0 lfbga64 8 x 8 1.7 str711fr1h6 128+16 32 str711fr2h6 256+16 64 str711fr0t6 64+16 16 lqfp64 10x10 str711fr1t6 128+16 32 str711fr2t6 256+16 64 str712fr0h6 64+16 16 no ye s 32 lfbga64 8 x 8 1.7 str712fr1h6 128+16 32 str712fr2h6 256+16 64 str712fr0t6 64+16 16 lqfp64 10 x10 str712fr1t6 128+16 32 str712fr2t6 256+16 64 str715fr0h6 64+16 16 no lfbga64 8 x 8 1.7 str715fr0t6 64+16 16 lqfp64 10 x 10
revision history str71xf 72/74 6 revision history table 41. document revision history date revision changes 17-mar-2004 1 first release 05-apr-2004 2 updated ?electrical parameters? on page 32 08-apr-2004 2.1 corrected str712f pinout. pins 43/42 swapped. 15-apr-2004 2.2 pdf hyperlinks corrected. 7-jul-2004 3 corrected description of stdby, v18, vss18 v18bkp vssbkp pins added iddrun typical data updated bspi max. baudrate. updated ?emi - memory interface? on page 55 29-oct-2004 4 corrected flash sector b1f0/f1 address in figure 6: memory map on page 29 corrected table 6 on page 23 lqfp64 test pin is 16 instead of 17. added to tqpfp64 column: pin 7 booten, pin 17 v 33io-pll changed description of jtck from ?external pull-down required? to ?external pull-up or pull down required?. 25-jan-2005 5 changed ?product preview? to ?preliminary data? on page 1 and 3 renamed ?pu/pd? column to ?reset state? in table 6 on page 23 added reference to str7 flash programming reference manual 19-apr-2005 6 added str715f devices and modified ram size of str71xf1 devices added bga package in section 3 updated ordering information in section 5 . added pll duty cycle min and max. in pll electrical characteristics on page 43
str71xf revision history 73/74 13-oct-2005 7 updated feature description on page 1 update overview section 1.1 added od/pp to p0.12 in ta bl e 6 changed name of wfi mode to wait mode changed memory map ta b l e 6 : ext. memory changed to 64 mb and flash register changed to 36 bytes. added power consumption ta b l e 1 4 modified bga144 f3, f5, f12 and g12 in ta b l e 2 and ta b l e 3 update emi timing ta bl e 2 5 and figure 29 22-may-2006 8 added flashless device. changed reset state of pins p1.10 and p1.13 from pu to pd, p0.15 from pu to floating and removed x in interrupt column for p1.15 and p1.12 in ta b l e 3 and ta bl e 6 added notes under ta bl e 3 on emi pin reset state. corrected inch value for d3 in figure 37 added footprint diagrams in figure 37 and figure 39 updated section 2: electrical parameters table 41. document revision history date revision changes
str71xf 74/74 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorize representative of st, st products are not designed, authorized or warranted for use in military, air craft, space, life saving, or life sustaining applications, nor in products or systems, where failure or malfunction may result in personal injury, death, or severe property or environmental damage. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2006 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com


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